The invention relates to clock recovery apparatus and methods, and more specifically to apparatus and methods for generating clock signals accurately locked to multi-gigabits-per-second data signals received over fiber optic channels.
Recently, the world has witnessed a phenomenal growth in the number of Internet users, applications and devices and in the amount of data traffic especially that of medium-rich contentxe2x80x94all demanding higher speed communications and connectivity over the Internet. To accommodate this demand, the Internet utilizes fiber optic channels for ultra high speed communications. The optical signals sent along the fiber optic channels are received by receivers that include both optical components and electrical components. The receivers convert the optical signals to electrical signals and send the converted electrical signals to electronic computer networks operating at lower speeds for processing data.
After an optical signal is converted to an electrical signal, a receiver recovers a clock signal and data within a clock and data recovery unit. A clock and data recovery unit typically includes a phase locked loop such as the phase locked loop 10 in FIG. 1. A phase locked loop is essential in synchronizing a clock signal with data received from the fiber optic channels. The phase locked loop 10 includes a phase detector 11, a charge pump 12, a filter 13, and a voltage controlled oscillator (VCO) 14. The purpose of a phase detector is to compare the phase of data (such as data 15) with that of a clock signal received from a VCO and determine whether the clock signal is ahead or retarded in comparison with the data. The charge pump 12 either provides current to the filter 13 or sinks current depending on the result of the comparison done by the phase detector. The filter 13 provides a voltage to the VCO 14 to either speed up or slow down the clock signal generated by the VCO 14. One of the major problems with the traditional non-tristate phase locked loops, however, is that when data includes a long stream of one""s or zero""s, the filter may continue to charge up causing the VCO frequency to drift. This could degrade the jitter performance or even result in bit errors in reading the data.
Accordingly, there is a need for a phase locked loop that is capable of maintaining a constant clock frequency during periods when the data includes a long stream of one""s or zero""s. The phase locked loop should be simple in its implementation to reduce the complexity, power consumption, and cost and should provide good jitter performance even at multi-gigabits-per-second data rates.
The present invention provides clock recovery methods and apparatus for maintaining a constant clock frequency during periods when multi-gigabits-per-second data signals received over fiber optic channels include a long stream of one""s or zero""s. In accordance with one embodiment, the present invention includes a phase detector for receiving and comparing a data signal and a clock signal, a one-shot unit for detecting a data transition, an XOR (exclusive OR) gate for generating an appropriate control signal in response to the output signals of the phase detector and the one-shot unit, a double-ended filter, a main differential charge pump for producing current, a compensating differential charge pump for producing additive or canceling current either to charge or discharge the filter or not to affect the filter, and a voltage controlled oscillator for generating the clock signal in response to the voltage level produced across the filter.
In accordance with one embodiment, the phase detector may be implemented with multiple D-flip flops. The one-shot unit may include a delay unit and an AND gate. The filter may include a resistor and a capacitor and further include a negative resistance amplifier. The main differential charge pump may receive input signals from the phase detector and produce double outputs. It may include cross-quading resistors, differential NPN input transistors, and a current source. The compensating differential charge pump may have its outputs coupled to the outputs of the main differential charge pump and receive input signals from the XOR. The compensating differential charge pump may also include differential NPN input transistors and a current source.
In an exemplary operation, when there is a data transition and if the clock signal and data signal are out of phase synchronization, then the compensating differential charge pump will add to or subtract from the filter charges that are equal in sign and quantity to those produced by the main differential charge pump. This is accomplished by adding the current produced by the compensating differential charge pump to the current produced by the main differential charge pump. The filter is then either charged or discharged and in turn the voltage controlled oscillator will speed up or slow down the clock signal it produces depending on whether the clock signal is advanced or retarded in phase compared to the data signal.
In another exemplary operation, when there is no data transition, the operation of the compensating differential charge pump will in effect cancel the operation of the main differential charge pump by producing a current that is equal in quantity but opposite in sign to the current produced by the main differential charge pump. In this case, the filter is neither charged nor discharged and in turn the speed of the clock signal or its frequency is maintained at the same level it was at the onset of the no data transition period.
According to the present invention, a method for recovering a clock signal from data may include receiving data and producing a clock signal, detecting a transition in the data, comparing the phase of the data to the phase of the clock signal, producing a charging or discharging current to the first end and second end of a filter when there is a data transition and if the clock signal and the data are out of phase synchronization, producing no charging or discharging current at the first and second ends of a filter when there is no data transition, speeding up the clock signal when there is a transition in the data and if the clock signal is retarded in phase compared to the data, slowing down the clock signal when there is a transition in the data and if the clock signal is advanced in phase compared to the data, and maintaining the speed or frequency of the clock signal at the level it was at the commencement of the no data transition period when there is no transition in the data.